1. Field of the Invention
The present invention relates to the fabrication of a dynamic random access memory (DRAMs) device, and more particularly, a fabrication technique for making microminiaturized storage capacitor used for charge storage.
2. Description of the Prior Art
Very large scale integration (VLSI) technologies have greatly increased the circuit density on the chip, and have significantly improved the circuit performance and reduced the cost of todays electronic products. Further improvement in the performance to cost ratio depends strongly on continued down scaling of these devices on a VLSI chip. One type of VLSI chip, the dynamic random access memory (DRAMs), is used extensively in the electronic industry and particularly in the computer industry for electrical data storage. These DRAM chips consist of an array of individual cells which store a unit of data (bit) and contain one charge passing transistor, usually a MOSFET, and a single storage capacitor. In the next 5 to 10 years the number of these cells, on a chip, are expected to reach 256 megabits per chip. To achieve these advances in data storage and maintain a reasonable chip size, the individual memory cells, on the chip, must be significantly reduced in size.
As these individual memory cells decrease in size, so must also the MOSFET charge passing transistor and the storage capacitor, decrease in size. However,the reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to noise level. Also, these smaller storage capacitor require shorter refresh cycle times to retain the necessary charge level.
When these microminiature capacitors are further reduced in size, it also becomes more difficult to improve the masking level tolerance and the etch tolerance required for manufacturing good memory chips. To avoid these problems, others have proposed methods for self-aligning the storage node contact of the capacitor to the device contact on the substrate. But they still require masking and etching to form the capacitor electrode structure. See for example, K. Jeong-Gyoo U.S. Pat. No. 5,155,056. The demanding tolerances associated with the mask alignment and etching, still remains as a problem that limits the size of these micro miniature capacitors.
Since it is important to provide a storage capacitor with the largest possible capacitance, it is very important to have not only the storage node contact aligned to the substrate, but to also have the capacitor electrode formed in a way that does not depend on these masking and etching tolerances.